1. Field of the Invention
This invention relates to a liquid crystal display panel of the type of active matrix drive in which every pixel has a storage capacitor.
2. Description of the Related Art
FIG. 9 is a diagram of an equivalent circuit of a conventional liquid crystal display panel, and FIG. 10 is a diagram of an equivalent circuit of a display pixel in the conventional liquid crystal display panel. In the conventional liquid crystal display panel 101, a plurality of data bus lines (signal lines) 102 are formed in parallel on one transparent glass substrate that is not shown, and a plurality of gate bus lines (scanning lines) 103 are formed thereon in an intersecting manner via an insulating film. Storage capacitor bus lines (for each of the rows) 104 are arranged in parallel with the gate bus lines 103, and a common storage capacitor bus line 105 is arranged at the ends on one side of the storage capacitor bus lines 104 in parallel with the data bus lines 102.
The storage capacitor bus lines 104 are each electrically connected to the common storage capacitor bus line 105. A predetermined potential is supplied from a storage capacitor bus line drive circuit (not shown) to the storage capacitor bus lines 104 through the common storage capacitor bus line 105.
Pixels are formed in the regions defined by the data bus lines 102 and the gate bus lines 103. Data drivers (signal line drive circuits) 106 and gate drivers (scanning line drive circuits) 107 are provided on the peripheral regions of the display region on one transparent glass substrate (not shown) on where the pixels are formed to drive the data bus lines 102 and the gate bus lines 103.
Referring to FIG. 10, a thin-film transistor (hereinafter abbreviated as TFT) 108 is formed near a point where the data bus line 102 and the gate bus line 103 intersect each other. The drain electrode D of the TFT 108 is connected to the data bus line 102, the gate electrode G of the TFT 108 is connected to the gate bus line 103, and the source electrode S of the TFT 108 is connected to a pixel electrode 109. A liquid crystal layer 111 is held between the pixel electrode 109 and an opposing electrode 110 thereby to form a liquid crystal capacitance Clc. A storage capacitor Cs is connected in parallel with the liquid crystal capacitance Clc. The storage capacitor Cs is formed between the pixel electrode 109 and the storage capacitor bus line 104. The opposing electrode 110 is formed on the other transparent glass substrate that is not shown. An opposing electrode voltage Vcom is applied to the opposing electrode 110.
In the conventional liquid crystal display panel of the active matrix drive type, by applying a signal voltage to each data bus line (signal line) 102, signal voltages of the pixels are applied to the liquid crystal capacitances Clc of a selected row in a state where one of the plurality of gate bus lines 103 is selected and a scanning signal is applied, so that the TFTs 108 connected to the selected gate bus line 103 are turned on. The liquid crystal capacitance Clc has such a small capacitance that it is not sufficient to hold the signal voltage. Therefore, the storage capacitor Cs is connected in parallel with the liquid crystal capacitance Clc, so that the voltage written into the pixel electrode will not fluctuate in one vertical period. Thus, brightness is prevented from changing in the vertical period to thereby prevent the occurrence of so-called flickering.
At the time when the gate bus line 103 is changed from on voltage greater than a gate threshold voltage of the TFT into off voltage lower than the gate threshold voltage of the TFT, the potential of the pixel electrode (liquid crystal capacitance) 109 fluctuates due to parasitic capacitance (Cgs) between the gate and the source of the TFT 108 and due to parasitic capacitance (Cgp) between the gate bus line 103 and the pixel electrode 109, often causing a fluctuation in the brightness in the panel and flickering. The effect, however, can be decreased by providing the storage capacitor Cs.
FIGS. 11A and 11B are diagrams showing a problem of the conventional liquid crystal display panel, wherein FIG. 11A is a diagram of an equivalent circuit illustrating the parasitic capacitances Ck formed at portions where the storage capacitor bus lines 104 intersect the data bus lines 102, and mixing of noise into the storage capacitor bus lines 104 through the parasitic capacitances Ck, and FIG. 11B is a diagram illustrating a change in the signal voltage of the data bus lines 102. FIG. 12 is a diagram concretely illustrating a display pattern in which a change in the voltage of the storage capacitor bus lines becomes a maximum.
As shown in FIGS. 11A and 11B, the storage capacitor bus lines 104 are arranged at right angles with the data bus lines 102 and, hence, parasitic capacitances Ck are formed at portions where the storage capacitor bus lines 104 intersect the data bus lines 102. Therefore, a change in the voltage of the data bus lines 102 is transmitted to the storage capacitor bus lines 104 via the parasitic capacitances Ck. As a result, noise mixes into the storage capacitor bus lines 104 causing the voltage of the storage capacitor bus lines 104 to fluctuate. The voltage of the pixel electrodes 109 fluctuates accompanying a fluctuation in the voltage of the storage capacitor bus lines 104, and there occurs display unevenness.
Though not shown in FIGS. 11A and 11B, the voltage of the storage capacitor bus lines 104 fluctuates like the above even due to a change in the signal voltage applied to the pixel electrodes 109 through the TFTs 108, often causing display unevenness.
In displaying a so-called checkered pattern in which “bright” and “dark” are alternately repeated for each of the pixels as shown in FIG. 12, in particular, the voltage greatly fluctuates on the storage capacitor bus lines 104, and display unevenness and the crosstalk become conspicuous.
When the checkered pattern shown in FIG. 12 is displayed by using the constitution in which the data drivers (signal line drive circuits) 106 alternately supply a positive signal and a negative signal as shown in FIG. 11A, noises mixing into the storage capacitor bus lines 104 through the parasitic capacitances Ck all become of the same phase since the voltages of the data bus lines 102 change all in the same direction, and a voltage fluctuation becomes the greatest on the storage capacitor bus lines 104.